TIRAMISU PhD student positions
The PhD project aims at novel, low-cost, ultra-low power open-source RISC-V-based accelerators augmented with reliability and safety features and tailored for edge AI applications. Energy efficiency is to be addressed by optimisation of the architecture, memory communication and the control. The lifetime and soft-error reliability aspect assumes architectural and physical design methodologies, as well as system-level improvements. For safety, the development of an infrastructure for in-field fault management of RISC-V-based systems to prevent catastrophic system failures, including fault and ageing detection and recovery mechanisms, using IJTAG for embedded instruments.
Recruitment host: Tallinn University of Technology, Tallinn, Estonia
Supervisors: Prof. Maksim Jenihhin, Dr. Artur Jutman
Cross-sectoral co-supervision: Dr. Juergen Alt, Infineon Technologies, Germany
Contact: Prof. Maksim Jenihhin, maksim.jenihhin@taltech.ee
More details at the host webpage:
The researcher of this PhD project will work on methods, strategies, and architectural enhancements aimed at improving the energy efficiency, latency, scalability and robustness of in-memory and near-memory AI processing and acceleration. He/she will experiment with ideas such as asynchronous event-based and dataflow processing, quantisation and model compression, brain-inspired modelling for algorithm-hardware co-optimisation, on-device adaptation, and other. The application scope of interest is (but not limited to) multimodal sensor-fusion with spiking and quantised neural networks on digital accelerators that use advanced nanoelectronics technologies.
Recruitment host: IMEC-NL, Eindhoven, Netherlands
Supervisors: Dr. Manolis Sifalakis, Dr. Amirreza Yousezadeh, Dr. Kanishkan Vadivel
Cross-sectoral co-supervision (PhD studies): Prof. Said Hamdioui, Delft University of Technology, Netherlands
Contact: Dr. Manolis Sifalakis, manolis.sifalakis@imec.nl
More details at the host webpage:
The PhD project aims to develop, design, and implement memristor-based in-memory computing edge AI engines. It will use analog computing for the key kernels of neural networks (multiply and accumulate operations) in which the memristors mimicking the synapse are structured in a compact crossbar architecture. To optimise the energy and enhance the reliability, different schemes will be explored, including different cell structures of the crossbar (e.g., 1T1R, 2T2R, 2T1R) while using crossbar-periphery codesign; current-based reading versus voltage-based reading of the crossbar, reliability aware mapping of the weights in the crossbar such as bits slicing, detection and recovery from read disturb which is a major concern for RRAM memristors, etc.
Recruitment host: Delft University of Technology, Delft, Netherlands
Supervisors: Prof. Said Hamdioui, Dr. Heba Abunahla
Cross-sectoral co-supervision: Dr. Amirreza Yousefzadeh, IMEC-NL, Netherlands
Contact: Prof. Said Hamdioui, s.hamdioui@tudelft.nl
This PhD project strives for the design and implementation of efficient, novel, AI inference-optimised mechanisms that detect random faults and enable recovery from them in order to improve the overall reliability and safety of digital edge devices. In addition, this thesis aims to analyse the contribution of the mechanism to failure probability reduction by using simulation, emulation and test chips by applying AI typical workloads. The starting point for the experiments is an existing autogenerated AI inference-optimised RISCV core from Infineon and industry-proven tools and methods for general hardening and fault analysis.
Recruitment host: Infineon Technologies, Munich, Germany
Supervisors: Prof. Wolfgang Ecker, Endri Kaja, Georg Georgakos
Cross-sectoral co-supervision (PhD studies): Prof. Maksim Jenihhin, Tallinn University of Technology, Estonia
Contact: Prof. Wolfgang Ecker, wolfgang.ecker@tum.de
This thesis aims for detection and recovery mechanisms for analog-devices in edge AI hardware. It shall evaluate mechanisms that can be integrated in analog edge AI platforms in order to improve their reliability and safety. Due to the different nature of analog circuits, the intended solutions for digital edge AI platforms of DC1.4 can usually not be reused except passing of deviation information to higher level functionalities. In-field mechanisms which are able to detect or compensate relevant deviations of circuit-specific parameters or performances shall be worked out. Similar to DC1.4, mechanisms to stress the analog hardware or to emulate relevant stress shall be implemented to enable verification of the developed assessment methods.
Recruitment host: Infineon Technologies, Munich, Germany
Supervisors: Mejri Jaafar, Dr. Jürgen Alt
Cross-sectoral co-supervision (PhD studies): Prof. Jaan Raik, Tallinn University of Technology, Estonia
Contact: Mejri Jaafar, jaafar.mejri@infineon.com
To develop a virtual environment that can emulate executable SW for all the different processors, including AI-capable ones, that equip modern control systems, each with different physical properties, computational needs, real-time challenges and accuracy requirements. To make sure that the specific characteristics of AI accelerators are properly addressed and modeled, including computing capabilities and parallelism, for example, tailoring the size of Multiply and Accumulate Units within Tensor Processing Unit accelerators.
Recruitment host: Dumarey Softronix, Turin, Italy
Supervisors: Alberto Pisoni
Cross-sectoral co-supervision (PhD studies): Dr. Sarah Azimi, Politecnico di Torino, Italy
Contact: Alberto Pisoni, alberto.pisoni@dumarey.com
More details at the host webpage:
In several domains it is crucial to estimate the real impact of faults in AI applications based on Neural Networks. Unfortunately, traditional methods are unfeasible due to the huge computational cost. The planned activities will focus on the development of efficient solutions to estimate the reliability of AI accelerators, considering the different kinds of (temporary and permanent) faults that can affect the hardware. Cross-layer approaches will be explored taking into account both the hardware characteristics and architecture and the different software layers composing the system. The goal is to devise solutions for trading-off estimation accuracy and computational power requirements.
Recruitment host: Politecnico di Torino, Turin, Italy
Supervisors: Prof. Matteo Sonza Reorda, Prof. Esteban Rodriguez
Cross-sectoral co-supervision: Dr. Alessandra Neri, Dumarey Softronix, Italy
Contact: Prof. Matteo Sonza Reorda, matteo.sonzareorda@polito.it
More details at the host webpage:
The PhD project focuses on improving the fault tolerance and safety of AI accelerators using innovative EDA methods. The selected AI accelerators will be analysed to assess their inherent fault tolerance and to identify safety critical components. The aim is to explore how hardware accelerators can be designed to incorporate high fault detection and correction mechanisms, and to identify areas where enhanced fault detection is required. Innovative methods to leverage EDA tool flows to efficiently detect and correct faults in AI accelerators will be developed, and traditional flows of existing Cadence tools and flows will be adapted to integrate AI capabilities.
Recruitment host: Cadence Design Systems, Munich, Germany
Supervisors: Dr. Hans-Martin Bluethgen, Dr. Ahmet Cagri Bagbaba
Cross-sectoral co-supervision (PhD studies): Prof. Matteo Sonza Reorda, Politecnico di Torino, Italy
Contact: Dr. Ahmet Cagri Bagbaba, abagbaba@cadence.com
More details at the host webpage:
The PhD project aims to explore and develop fault models using EDA tools, explore safety analysis methodologies using functional testing techniques, or use metric-driven verification methodologies for AI accelerators. The project will also exploit and optimise safety verification techniques such as simulation-based fault injection or formal verification techniques. The solutions will be integrated into the overall EDA tool flow to provide an advanced methodology flow incorporating EDA practices to optimise safety and accelerate time-to-market for AI accelerator designs.
Recruitment host: Cadence Design Systems, Munich, Germany
Supervisors: Dr. Hans-Martin Bluethgen, Dr. Felipe Augusto da Silva
Cross-sectoral co-supervision (PhD studies): Prof. Said Hamdioui, Delft University of Technology, Netherlands
Contact: Dr. Ahmet Cagri Bagbaba, abagbaba@cadence.com
More details at the host webpage:
The performance of AI accelerators often highly influenced by the memory interface. With new packaging approaches like Chiplets or 3D integration, a new concept for high-bandwidth memory integration between the memory and the AI accelerator can be explored. This PhD project aims to develop a disruptive concept of memory integration based on advanced packaging options. It will consider the development of a highly innovative design methodology for fast and easy design of different memory integration options based on different package types.
Recruitment host: Fraunhofer-Gesellschaft, Dresden, Germany
Supervisors: Dr. Benjamin Prautsch, Andy Heinig
Cross-sectoral co-supervision: Dr. Felipe Augusto da Silva, Cadence Design Systems, Germany
Co-supervision (PhD studies): Prof. Said Hamdioui, Delft University of Technology, Netherlands
Contact: Andy Heinig, andy.heinig@eas.iis.fraunhofer.de
Optimisation of ANN models for EdgeAI typically targets model size reduction, minimal energy consumption, maximum performance, while considering accuracy constraints dictated by the application. The DC will (i) explore how leveraging the spatiotemporal domain (i.e., spatial and temporal information) can enhance the performance and robustness of emerging DNN models (such as transformer networks) in time-series and vision Edge AI applications, by dynamically adapting the data flow and connectivity of DNN layers (i.e. early exits), and (ii) use hardware and technology metrics to develop a holistic approach (potentially through neural architecture search) that combines efficiency and robustness, aiming to address both challenges simultaneously.
Recruitment host: University of Cyprus, Nicosia, Cyprus
Supervisors: Prof. Theocharis Theocharides, Dr. Christos Kyrkou
Cross-sectoral co-supervision: Dr. Amirreza Yousefzadeh, IMEC-NL, Netherlands
Contact: Prof. Theocharis Theocharides, ttheocharides@ucy.ac.cy
Dynamic neural networks exhibit different behaviour for every input during inference. Further, transformer models, and integration of attention contributed towards extremely effective machine learning models, where dynamicity is only recently being adopted. This DC will work to (i) integrating context as an attention mechanism in transformers, to reduce amount of input data; develop a framework to quantify and evaluate the reliability (in terms of hardware faults) of dynamic NNs and transformers in a deterministic manner; and (iii) formulate a holistic neural architecture search that combines efficiency and reliability, while adhering to Edge AI constraints.
Recruitment host: University of Cyprus, Nicosia, Cyprus
Supervisors: Prof. Maria K. Michael, Prof. Theocharis Theocharides
Cross-sectoral co-supervision: Dr. Felipe Augusto da Silva, Cadence Design Systems, Germany
Contact: Prof. Theocharis Theocharides, ttheocharides@ucy.ac.cy
The wide adoption of AI model inference was boosted by the availability of efficient hardware accelerators (e.g., GPUs and TPUs). This proposal focuses on the identification of practical techniques able to reduce the failure probability of these accelerators due to hardware faults, possibly at the expenses of a slight reduction in the achieved performance. Acting on the hardware (which is often used also in less critical applications) is often not a viable approach. Hence, the proposed activity aims at investigating methods to harden AI-based inference acting on their software implementation, taking into account the underlying hardware architecture.
Recruitment host: Politecnico di Torino, Turin, Italy
Supervisors: Prof. Luca Sterpone, Dr. Sarah Azimi
Cross-sectoral co-supervision: Dr. Ahmet Cagri Bagbaba, Cadence Design Systems, Germany
Contact: Prof. Luca Sterpone, luca.sterpone@polito.it
More details at the host webpage:
The PhD project aims to develop a neural architecture search (NAS) framework for designing an efficient, robust, and reliable hybrid CNN-Transformer supernetwork capable of generating distinct subnetworks specialised for various HW platforms without extensive retraining. The research objectives include: a) investigating existing and introducing novel training algorithms to enhance the robustness, reliability, and accuracy of the subnetworks within the supernetwork; b) developing fast and efficient search engine algorithms for extracting subnetworks from the trained supernetwork; c) training surrogate predictor models to evaluate key metrics such as accuracy, robustness, reliability, and latency for full-precision and quantised sub-networks.
Recruitment host: Tallinn University of Technology, Tallinn, Estonia
Supervisors: Prof. Masoud Daneshtalab, Prof. Maksim Jenihhin
Cross-sectoral co-supervision: Prof. Wolfgang Ecker, Infineon Technologies, Germany
Contact: Prof. Masoud Daneshtalab, masoud.daneshtalab@taltech.ee
In this PhD project, the researcher will develop non-ideality/reliability aware mapping and quantisation schemes to tolerate the impact of memristive devices non-ideality on the computational accuracy without compromising on energy efficiency. Non-idealities-aware training schemes will also be investigated. They will also explore dynamic neural network models to dynamically deal with memristive non-idealities; different schemes, such as mapping defective cell/row to a redundant cell/row, defective cell/block disabling schemes, will be explored and their impact on the model’s accuracy and energy-efficiency will be studied.
Recruitment host: Delft University of Technology, Delft, Netherlands
Supervisors: Prof. Said Hamdioui, Dr. Heba Abunahla
Cross-sectoral co-supervision: Dr. Manolis Sifalakis, IMEC-NL, Netherlands
Contact: Prof. Said Hamdioui, s.hamdioui@tudelft.nl
The PhD project studies the role of human oversight in Edge AI system design and derive classifications of the developed/envisioned Edge AI system along the risk categories of the EU AI Act. It ties into more technical PhD projects by providing a risk assessment to ensure Risk Mitigation activities are met, specifically on data governance, technical documentation and traceability, transparency, human oversight, accuracy and robustness of AI system characteristics and interactions. Expected results will address the explainability needs of different stakeholders, deliver recommendations for human-centric Edge AI applications, and derive blueprints for Edge AI system implementation strategies.
Recruitment host: Bern University of Applied Science, Switzerland
Supervisors: Prof. Christian Hopp, Prof. Branka Hadji Misheva
Cross-sectoral co-supervision: Dr. Manolis Sifalakis, IMEC-NL, Netherlands
Co-supervision (PhD studies): Prof. Claudia Werker, Delft University of Technology, Netherlands
Contact: Prof. Christian Hopp, christian.hopp@bfh.ch
The PhD project studies innovative Edge AI software/hardware solution design from early-stage research to patenting, technology transfer, or relevant commercialisation options. It develops an organisational and interaction model that meets the requirements of the EU’s framework for Responsible Research and Innovation. Results provide commercialisation and valorisation actions for major exploitable research results and derive suitable approaches towards the stakeholders’ groups with the highest capacity for market application. The project will provide novel insights for stakeholder impact assessment balancing innovation speed and AI risk assessment.
Recruitment host: Bern University of Applied Science, Switzerland
Supervisors: Prof. Christian Hopp, Prof. Gernot Pruschak
Cross-sectoral co-supervision: Alberto Pisoni, Dumarey Softronix, Italy
Co-supervision (PhD studies): Prof. Alessandra Colombelli, Politecnico di Torino, Italy
Contact: Prof. Christian Hopp, christian.hopp@bfh.ch
