Training and Innovation in Reliable and Efficient Chip Design for Edge AI

TIRAMISU “Training and Innovation in Reliable and Efficient Chip Design for Edge AI” is a European HORIZON MSCA Doctoral Network project. The general research objective of TIRAMISU is a practical methodology for reliable and energy-efficient Edge AI hardware backbone design and innovation management. The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. The consortium is strategically designed to foster cross-disciplinary synergies, by seamlessly integrating innovation management research with the technical aspects of Edge AI design. The non-academic sector is represented by a European flagship R&D hub for nanoelectronics - IMEC, a global leader in industrial electronics and the largest semiconductor manufacturer in Germany - Infineon, a trusted automotive solutions provider - Dumarey, the worldwide leader in EDA tools development - Cadence. The academic excellence is established by the top ICT and Technology Innovation engineering universities and Europe's largest application-oriented research organisation - Fraunhofer.

Project duration: September 1, 2024 - August 31, 2028 (4 years)

Total budget: 4.37 MEUR

Doctoral candidates: 17 researchers recruited for 36 months

Application process: September 1 - October 31, 2024 (early application encouraged)

All DCs are planned to start in December 2024 - February 2025.